1. Field of the Invention
The present invention relates to a ring oscillator. In particular, the present invention discloses a ring oscillator whose output signal is not affected by the characteristics of MOS devices.
2. Description of the Prior Art
In modern information society, a digital system capable of processing digital data needs a clock signal to arbitrate and coordinate timings associated with processing and transmission of the digital data. Therefore, an oscillator used to generate the required clock signal becomes a fundamental component in a modern digital circuit. In addition, a phase lock loop (PLL) of signal processing circuits used in a general communication system, an optical disk drive, and a hard-disk drive commonly applies a voltage-controlled oscillator (VCO). That is, voltages are used to control a voltage-controlled oscillator to make the clock signal have a specific period or a specific frequency. With the improvement of transmission and processing speeds for digital signals, it becomes an important issue to manufacture oscillators that are capable of generating high-frequency (short period) clock signals.
Please refer to FIG. 1, which is a diagram of a prior art ring oscillator 10. The ring oscillator 10 has a plurality of delay cells cascaded to form a closed loop. Please note that only three delay cells 12a, 12b, 12c are shown in FIG. 1 for simplicity. Operation of the delay cells 12a, 12b, 12c are similar to that of an inverter, and functionality of the delay cells 12a, 12b, 12c are to make input ports IP1, IP2, IP3 and related output ports OP1, OP2, OP3 correspond to opposite voltage levels. For example, when the input port IP1 corresponds to a high voltage level, the corresponding output port OP1 corresponds to a low voltage level; on the other hand, when the input port IP1 corresponds to the low voltage level, the corresponding output port OP1 corresponds to the high voltage level.
Operation of the ring oscillator 10 is described as follows. When the input port IP1 of the delay cell 12a corresponds to the high voltage level, the output port OP1 of the delay cell 12a corresponds to the low voltage level. Because the output port OP1 of the delay cell 12a is electrically connected to input port IP2 of the following delay cell 12b, the input port IP2 of the delay cell 12b, therefore, corresponds to the low voltage level. The output port OP2 of the delay cell 12b then corresponds to the high voltage level. Similarly, because output port OP2 of the delay cell 12b is electrically connected to input port IP3 of the following delay cell 12c, the input port IP3 of the delay cell 12c corresponds to the high voltage level for driving output port OP3 of the delay cell 12c to correspond to the low voltage level.
It is noteworthy that output port OP3 of the delay cell 12c is electrically connected to the input port IP1 of the delay cell 12a, and the input port IP1 initially corresponds to the high voltage level. However, the closed loop formed by the delay cells 12a, 12b, 12c forces the input port IP1 of the delay cell 12a to correspond to the low voltage level after the delay cells 12a, 12b, 12c sequentially operate. After input port of each delay cell 12a, 12b, 12c receives an input signal, the corresponding delay cell requires a delay time Td to generate an output signal having a voltage level opposite to that of the input signal. Therefore, voltage level at the output port and input port of each delay cell 12a, 12b, 12c has a level transition every three delay time 3*Td.
The level transition means that the voltage level transits from the original high voltage level to the low voltage level or the voltage level transits from the original low voltage level to the high voltage level. In other words, the period of the clock signal F0 generated from the ring oscillator 10 becomes 6*Td. In addition, the control voltage Vc is used to adjust the delay time of each delay cell 12a, 12b, 12c. Therefore, period of the clock signal F0 is controllable with the adjustment of the voltage value of the control voltage Vc.
Please refer to FIG. 2, which is a diagram of the delay cell 12a shown in FIG. 1. The delay cell 12a includes a plurality of p-channel metal oxide semiconductor (PMOS) transistors 14a, 14b, and a plurality of n-channel metal oxide semiconductor (NMOS) transistors 16a, 16b. The transistors 14a, 14b, 16a, 16b are fabricated according to a CMOS semiconductor process. The transistors 14a, 16a are matched to correspond to the same transistor characteristics such as an identical doping concentration, an identical channel width/length ratio, etc. In addition, the transistors 14b, 16b are matched as well.
The transistors 14a, 16a function as current sources. That is, the transistors 14a, 16a operate in a saturation region. Therefore, when a control voltage Vc1 is inputted into a gate of the transistor 14a, a fixed reference current I1 flowing from a voltage source Vdd (high voltage level) toward the transistor 14b is generated. Similarly, when a control voltage Vc2 is inputted into a gate of the transistor 16a, a fixed reference current I2 flowing from the transistor 16b toward a voltage source Vss (low voltage level) is generated.
Operation of the delay cell 12a is briefly described as follows. If the input port IP1 corresponds to a high voltage level, the transistor 16b is turned on, and the transistor 14b is turned off. Therefore, the reference current I2 starts discharging the output port OP1 to make the output port OP1 correspond to the low voltage level.
As mentioned above, when the delay cell 12c operates, the level transition occurs at the input port IP1 of the delay cell 12a. Therefore, after the voltage level of the input port IP1 transits from the high voltage level to the low voltage level, the transistor 14b is turned on, and the transistor 16b is then turned off. The reference current I1, therefore, begins charging the output port OP1 to make the output port OP1 correspond to the high voltage level. In other words, the transistors 14b, 16b function as switches used to determine that the output port OP1 needs to be charged or discharged according to the voltage level of the input port IP1. Then, the voltage levels of the output port OP1 and the input port IP1 correspond to opposite voltage levels.
In addition, the magnitudes of the reference currents I1, I2 affect the delay time Td of the delay cell 12a. If the reference current I1 is increased, the reference current I1 raises the voltage level of the output port OP1 much quicker. Similarly, if the reference current I2 is increased, the reference current I2 decreases voltage level of the output port OP1 much quicker. Please note that the magnitudes of the reference currents I1, I2 are dominated by the control voltages Vc1, Vc2. As shown in FIG. 1, the control voltage Vc generating the control voltages Vc1, Vc2 is then capable of adjusting the delay time Td to alter period of the clock signal F0.
However, with regard to the transistors 14a, 16a, the transistor characteristics varies with the operating temperature, voltage sources Vdd, Vss, etc. For instance, when the operating temperature increases, mobility of electrons in the transistors 14a, 16a is suppressed. Therefore, under the same gate-to-source bias, current values of the reference currents I1, I2 decrease owing to an increase of the operating temperature. On the other hand, when the operating temperature decreases, mobility of the electrons in the transistors 14a, 16a is improved. Therefore, under the same gate-to-source bias, current values of the reference currents I1, I2 increase owing to a decrease of the operating temperature. In other words, if the operating temperature varies randomly, the period of the clock signal F0 accordingly becomes unstable. That is, the frequency of the clock signal F0 deviates from an ideal target value. Besides, the unstable voltages provided by the voltage sources Vdd, Vss alter gate-to-source biases of the transistors 14a, 16a so that the magnitudes of the reference currents I1, I2 varies. Similarly, the period of the clock signal F0 varies accordingly and deviates from the ideal target value. To sum up, transistor characteristics of the transistors influence the frequency of the clock signal F0 so that the clock signal F0 becomes unstable.
It is therefore a primary objective of this invention to provide a ring oscillator whose output signal is not affected by transistor characteristics of MOS devices.
Briefly summarized, the preferred embodiment of the claimed invention discloses a bias circuit of a ring oscillator for driving the ring oscillator to output a clock signal with a predetermined period. The ring oscillator has a plurality of delay cells. Each two adjacent delay cells are cascaded in series with an output port of a leading delay cell and an input port of a following delay cell being connected. An input port of a first delay cell within the delay cells is electrically connected to an output port of a last delay cell within the delay cells.
Each delay cell includes a first driving transistor for outputting a first bias current to drive a voltage at an output port of the delay cell to correspond to a first logic level, a second driving transistor for outputting a second bias current to drive the voltage at the output port of the delay cell to correspond to a second logic level, and a switch circuit electrically connected to the first driving transistor and the second driving transistor for deciding whether the output port of the delay cell is electrically connected to either the first driving transistor or the second driving transistor according to a voltage at an input port of the delay cell.
The bias circuit has a first loading unit including a p-n junction and a second loading unit including a p-n junction where the area of the p-n junction of the second loading unit is not equal to the area of the p-n junction of the first loading unit, a first reference circuit, a resistor electrically connected between the p-n junction of the second loading unit and a second current mirror circuit, and a second reference circuit electrically connected to the first reference circuit for establishing a current mirror connection used to make a current transmitted by the second reference circuit and the currents transmitted by the first current mirror and the second current mirror circuit correspond to a first predetermined ratio.
The first reference circuit has the first current mirror circuit electrically connected to the p-n junction of the first loading unit, and the second current mirror circuit symmetric to the first current mirror circuit. The second current mirror is electrically connected to the first current mirror circuit for establishing a current mirror connection used to make the first current mirror circuit and the second current mirror circuit respectively transmit currents with an identical current value to drive the corresponding first loading unit and the second loading unit. The first reference circuit is electrically connected to the first driving transistor of each delay cell for establishing a current mirror used to make the first bias current and the currents transmitted by the first current mirror and the second current mirror circuit correspond to a second predetermined ratio. The second reference circuit is electrically connected to the second driving transistor of each delay cell for establishing a current mirror used to make the second bias current and the currents transmitted by the first current mirror and the second current mirror circuit correspond to a third predetermined ratio.
It is an advantage of the present invention that the claimed ring oscillator makes use of the intrinsic band gap associated with a p-n junction to control a bias current. The claimed ring oscillator adopts either two diodes or two BJTs whose p-n junctions correspond to different areas, and then generates the bias current through different voltage difference caused by the unmatched p-n junctions. In addition, a resistor having a positive temperature coefficient is also utilized to compensate variation of the bias current caused by an unsteady temperature. The claimed ring oscillator then utilizes the bias current and established current mirror connection to provide each delay cell with a desired reference current. Therefore, the reference current is fixed even though transistor characteristics of any MOS transistor within the claimed ring oscillator is unsteady. In other words, the claimed ring oscillator is capable of outputting a stable clock signal.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.